JPH031834B2 - - Google Patents

Info

Publication number
JPH031834B2
JPH031834B2 JP58195643A JP19564383A JPH031834B2 JP H031834 B2 JPH031834 B2 JP H031834B2 JP 58195643 A JP58195643 A JP 58195643A JP 19564383 A JP19564383 A JP 19564383A JP H031834 B2 JPH031834 B2 JP H031834B2
Authority
JP
Japan
Prior art keywords
forming
substrate
electrodes
protruding
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58195643A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6086854A (ja
Inventor
Hiroshi Takahashi
Isamu Kitahiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58195643A priority Critical patent/JPS6086854A/ja
Publication of JPS6086854A publication Critical patent/JPS6086854A/ja
Publication of JPH031834B2 publication Critical patent/JPH031834B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58195643A 1983-10-19 1983-10-19 突起電極形成用基板及びその製造方法 Granted JPS6086854A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58195643A JPS6086854A (ja) 1983-10-19 1983-10-19 突起電極形成用基板及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58195643A JPS6086854A (ja) 1983-10-19 1983-10-19 突起電極形成用基板及びその製造方法

Publications (2)

Publication Number Publication Date
JPS6086854A JPS6086854A (ja) 1985-05-16
JPH031834B2 true JPH031834B2 (en]) 1991-01-11

Family

ID=16344579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58195643A Granted JPS6086854A (ja) 1983-10-19 1983-10-19 突起電極形成用基板及びその製造方法

Country Status (1)

Country Link
JP (1) JPS6086854A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61260648A (ja) * 1985-05-15 1986-11-18 Matsushita Electric Ind Co Ltd 半導体装置の実装方法

Also Published As

Publication number Publication date
JPS6086854A (ja) 1985-05-16

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